Module Definition
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Module : dti_mux21
SCORELINECONDTOGGLEFSMBRANCHASSERT
88.89 100.00 66.67 100.00

Source File(s) :
/nfs_project/gemini/DV/nadeem/dv/main_regression_08_dec_2022/gemini/lib/tm16_pvt/dti_tm16ffc_16f96_9t_stdcells_rev1p0p1_pwr.v

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst35.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst47.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst48.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst53.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst59.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst60.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst98.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst104.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst107.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst109.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst142.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst161.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst166.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst168.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst202.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst229.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst236.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst237.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst246.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst248.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst253.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst257.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst259.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst265.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst276.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst278.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst282.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst306.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst314.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst320.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst324.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst327.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst349.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst351.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst355.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst358.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst360.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst361.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst377.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst383.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst386.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst394.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst402.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst408.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst413.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst440.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst453.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst470.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst512.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst542.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst554.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst568.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst578.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst594.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst601.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst608.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst611.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst617.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst629.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst654.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst660.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst664.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst669.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst675.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst702.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst704.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst718.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst720.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst721.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst722.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst724.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst735.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst751.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst758.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst786.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst809.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst826.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst866.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst868.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst879.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst907.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst927.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst930.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst934.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst951.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst964.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst967.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst968.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst979.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst983.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1015.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1017.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1026.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1037.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1043.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1055.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1078.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1109.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1110.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1118.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1127.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1130.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1133.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1172.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1179.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1181.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1196.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1203.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1212.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1232.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1237.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1243.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1254.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1267.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1269.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1287.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1295.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1330.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1344.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1351.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1369.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1374.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1376.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1423.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1428.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1430.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1436.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1444.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1454.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1461.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1484.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1488.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1495.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1506.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1512.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1514.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1522.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1554.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1561.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1581.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1590.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1592.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1602.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1605.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1611.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1629.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1636.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1646.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1652.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1669.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1673.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1677.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1701.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1705.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1706.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1723.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1724.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1752.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1760.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1763.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1783.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1807.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1835.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1837.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1859.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1871.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1875.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1887.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1892.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1896.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1922.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1927.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1930.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1938.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1939.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1944.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1958.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1964.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1979.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1980.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1991.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1992.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst1997.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2020.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2035.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2061.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2065.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2081.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2099.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2100.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2151.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2162.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2211.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2223.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2228.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2229.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2230.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2239.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2257.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2292.xdti_16f_9t_96_ckmux21.xmux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2313.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2316.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2321.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2400.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2423.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2432.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2434.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2439.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2441.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2459.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2464.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2472.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2477.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2484.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2485.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2488.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2510.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2511.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2513.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2572.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2574.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2583.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2590.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2603.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2657.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2690.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2705.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2713.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2721.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2724.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2734.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2752.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2776.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2782.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2786.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2791.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2799.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2820.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2847.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2875.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2878.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2879.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2889.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2897.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2927.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2968.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2971.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2975.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst2993.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3001.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3011.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3034.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3040.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3043.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3058.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3059.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3103.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3120.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3133.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3142.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3157.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3169.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3179.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3180.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3187.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3191.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3210.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3211.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3222.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3236.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3245.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3290.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3296.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3329.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3338.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3347.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3357.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3382.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3383.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3401.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3422.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3425.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3426.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3427.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3432.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3435.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3443.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3474.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3477.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3482.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3502.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3516.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3555.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3556.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3557.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3584.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3590.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3601.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3630.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3653.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3660.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3682.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3689.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3697.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3721.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3726.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3760.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3770.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3780.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3781.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3798.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3800.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3801.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3806.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3809.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3826.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3829.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3836.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3844.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3874.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3875.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3879.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3882.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3883.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3887.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3917.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3922.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3928.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3936.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3942.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3945.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3961.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3966.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3984.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3987.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3989.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst3998.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4011.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4021.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4023.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4055.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4058.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4060.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4064.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4068.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4075.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4078.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4084.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4088.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4092.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4114.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4118.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4128.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4139.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4170.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4175.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4194.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4196.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4214.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4241.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4253.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4256.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4257.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4278.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4293.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4300.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4302.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4309.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4316.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4332.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4333.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4342.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4365.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4368.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4370.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4373.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4390.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4433.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4454.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4484.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4487.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4503.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4566.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4589.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4604.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4610.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4616.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4619.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4624.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4634.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4639.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4643.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4644.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4660.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4668.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4718.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4726.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4780.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4793.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4826.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4828.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4829.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4830.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4833.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4857.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4861.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4865.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4868.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4903.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4905.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4915.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4928.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4931.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4943.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4946.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4950.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4954.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4965.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4974.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4981.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst4984.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5004.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5012.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5013.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5024.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5043.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5057.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5093.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5095.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5099.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5100.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5101.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5116.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5167.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5171.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5176.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5180.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5187.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5200.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5206.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5209.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5210.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5212.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5228.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5237.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5238.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5287.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5297.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5302.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5305.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5309.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5317.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5318.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5328.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5349.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5364.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5379.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5384.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5397.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5402.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5407.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5415.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5419.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5423.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5429.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5431.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5465.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5477.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5491.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5501.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5508.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5515.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5550.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5558.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5586.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5592.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5606.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5616.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5625.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5628.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5643.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5666.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5669.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5672.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5687.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5694.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5710.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5724.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5760.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5761.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5764.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5767.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5772.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5786.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5819.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5844.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5847.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5850.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5851.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5865.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5871.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5919.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5923.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5925.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5937.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5942.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5960.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5974.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5980.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5983.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst5988.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6003.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6022.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6045.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6059.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6093.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6110.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6120.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6125.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6142.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6145.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6152.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6167.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6199.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6201.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6208.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6233.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6239.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6261.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6272.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6312.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6322.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6328.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6333.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6341.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6353.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6369.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6370.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6376.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6384.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6396.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6416.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6450.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6455.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6472.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6476.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6501.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6504.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6512.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6526.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6527.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6529.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6550.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6551.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6555.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6558.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6565.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6571.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6594.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6598.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6606.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6613.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6614.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6626.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6627.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6669.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6687.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6716.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6728.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6730.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6839.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6840.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6841.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6860.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6869.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6876.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6883.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6887.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6897.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6900.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6936.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6959.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6967.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6981.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst6987.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7005.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7036.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7041.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7049.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7059.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7071.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7101.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7104.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7107.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7123.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7132.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7147.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7157.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7165.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7168.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7180.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7183.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7189.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7191.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7202.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7207.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7224.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7225.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7235.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7260.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7275.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7290.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7300.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7323.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7328.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7330.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7337.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7356.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7365.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7381.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7385.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7389.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7398.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7402.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7409.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7420.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7433.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7438.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7449.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7458.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7467.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7482.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7509.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7525.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7528.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7542.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7543.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7552.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7560.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7574.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7592.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7632.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7645.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7678.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7687.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7725.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7731.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7759.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7766.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7790.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7807.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7828.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7834.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7846.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7864.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7865.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7866.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7880.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7881.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7893.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7906.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7907.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7917.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7920.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7923.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst7945.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8002.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8008.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8014.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8030.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8034.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8055.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8066.xdti_16f_9t_96_ckmux21.xmux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8068.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8070.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8090.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8092.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8096.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8099.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8103.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8152.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8153.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8175.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8178.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8183.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8198.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8207.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8213.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8223.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8235.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8248.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8272.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8281.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8326.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8327.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8333.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8353.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8395.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8416.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8435.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8438.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8450.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8478.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8487.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8514.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8516.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8522.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8542.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8548.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8564.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8567.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8579.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8589.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8616.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8627.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8629.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8638.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8645.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8651.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8666.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8668.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8672.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8677.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8691.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8713.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8714.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8726.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8748.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8750.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8768.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8779.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8806.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8831.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8833.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8865.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8868.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8886.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8899.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8900.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8916.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8921.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8935.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8940.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8945.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8947.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8953.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8954.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8955.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8960.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8967.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8968.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8971.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8981.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8985.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst8998.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9009.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9014.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9019.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9025.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9030.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9033.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9046.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9056.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9082.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9085.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9091.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9103.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9107.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9111.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9120.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9123.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9126.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9136.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9162.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9167.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9192.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9203.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9204.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9215.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9231.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9235.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9245.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9246.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9251.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9262.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9285.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9288.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9292.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9311.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9347.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9360.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9376.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9385.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9416.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9420.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9427.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9428.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9433.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9438.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9455.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9456.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9461.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9477.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9490.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9502.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9503.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9507.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9511.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9533.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9542.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9548.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9550.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9554.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9573.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9583.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9597.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9599.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9603.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9607.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9624.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9637.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9663.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9687.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9691.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9703.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9704.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9709.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9714.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9731.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9735.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9747.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9755.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9788.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9791.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9800.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9813.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9815.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9820.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9851.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9857.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9880.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9892.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9899.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9922.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9924.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9933.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9938.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9940.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9941.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9946.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9953.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9957.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9959.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9961.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9970.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9976.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9977.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9980.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst9989.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10001.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10012.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10025.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10033.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10035.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10050.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10058.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10067.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10069.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10074.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10075.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10077.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10083.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10123.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10127.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10131.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10153.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10156.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10161.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10167.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10188.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10201.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10209.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10220.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10238.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10244.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10245.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10246.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10258.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10284.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10293.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10295.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10312.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10325.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10327.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10336.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10347.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10353.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10366.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10389.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10405.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10411.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10413.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10414.xdti_16f_9t_96_ckmux21.xmux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10430.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10431.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10462.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10466.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10499.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10504.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10512.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10520.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10529.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10579.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10580.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10593.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10597.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10598.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10608.xdti_16f_9t_96_ckmux21.xmux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10609.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10617.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10637.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10639.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10645.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10655.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10671.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10673.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10677.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10678.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10681.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10689.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10695.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10702.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10705.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10711.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10716.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10722.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10730.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10738.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10747.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10752.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10759.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10763.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10770.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10783.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10817.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10836.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10838.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10843.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10847.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10849.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10860.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10892.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10893.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10911.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10912.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10917.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10925.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10935.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10972.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10977.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst10997.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11022.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11062.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11065.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11068.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11079.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11088.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11089.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11090.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11101.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11108.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11110.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11112.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11133.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11139.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11162.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11163.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11180.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11184.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11195.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11229.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11238.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11240.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11248.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11266.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11274.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11278.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11282.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11297.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11301.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11314.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11324.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11329.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11333.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11334.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11338.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11341.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11356.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11358.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11371.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11383.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11393.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11403.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11412.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11433.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11435.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11437.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11441.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11444.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11458.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11476.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11480.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11483.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11517.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11538.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11553.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11562.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11565.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11566.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11568.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11577.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11584.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11588.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11612.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11624.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11625.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11636.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11639.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11645.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11653.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11657.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11667.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11704.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11715.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11727.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11735.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11740.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11743.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11750.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11760.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11763.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11802.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11806.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11814.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11823.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11824.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11828.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11841.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11842.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11849.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11850.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11860.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11863.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11864.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11875.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11885.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11893.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11920.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11924.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11927.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11950.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11953.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11971.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst11993.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12026.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12028.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12047.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12082.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12094.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12098.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12104.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12110.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12125.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12127.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12143.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12151.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12156.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12180.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12189.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12215.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12232.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12233.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12235.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12249.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12267.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12284.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12285.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12315.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12328.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12339.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12353.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12363.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12403.xdti_16f_9t_96_ckmux21.xmux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12410.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12411.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12415.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12429.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12446.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12466.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12519.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12532.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12546.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12569.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12592.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12600.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12618.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12630.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12638.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12652.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12717.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12720.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12755.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12761.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12763.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12777.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12778.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12781.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12782.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12791.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12792.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12812.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12813.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12826.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12827.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12851.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12867.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12869.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12870.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12889.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12890.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12894.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12902.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12908.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12923.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12929.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12952.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12972.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst12976.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13009.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13022.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13038.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13042.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13054.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13057.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13062.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13063.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13065.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13067.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13073.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13083.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13091.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13109.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13113.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13117.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13147.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13160.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13180.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13195.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13211.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13219.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13243.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13248.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13256.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13260.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13272.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13291.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13327.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13328.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13337.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13359.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13372.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13373.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13386.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13389.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13397.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13400.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13407.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13425.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13427.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13435.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13437.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13449.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13453.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13501.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13548.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13580.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13588.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13610.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13617.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13636.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13639.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13640.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13642.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13662.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13663.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13666.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13677.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13686.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13687.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13692.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13701.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13702.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13718.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13745.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13746.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13751.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13755.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13756.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13764.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13767.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13773.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13780.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13798.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13804.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13807.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13824.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13836.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13846.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13852.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13888.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13890.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13892.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13915.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13939.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13951.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13959.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13964.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13967.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13969.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13980.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13993.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13998.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst13999.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14054.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14056.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14066.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14072.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14076.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14085.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14105.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14118.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14169.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14175.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14194.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14198.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14217.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14222.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14229.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14244.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14271.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14272.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14273.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14296.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14308.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14312.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14318.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14328.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14338.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14344.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14354.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14376.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14381.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14403.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14407.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14409.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14448.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14454.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14477.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14523.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14539.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14549.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14561.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14588.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14617.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14623.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14662.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14676.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14677.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14686.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14742.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14751.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14763.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14769.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14784.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14789.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14816.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14831.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14832.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14841.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14866.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14867.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14871.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14875.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14897.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14906.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14908.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14929.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14942.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14948.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14961.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14966.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14987.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14994.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst14999.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15022.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15036.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15062.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15069.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15077.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15125.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15133.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15134.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15149.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15173.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15180.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15185.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15186.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15189.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15193.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15207.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15217.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15227.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15235.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15239.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15248.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15254.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15269.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15309.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15322.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15323.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15334.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15346.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15372.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15386.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15397.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15402.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15431.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15440.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15446.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15461.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15489.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15504.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15516.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15546.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15558.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15565.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15586.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15587.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15589.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15638.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15646.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15655.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15671.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15672.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15680.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15695.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15697.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15706.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15709.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15714.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15721.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15724.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15738.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15743.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15749.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15751.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15754.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15758.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15796.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15803.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15806.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15816.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15836.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15837.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15840.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15844.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15891.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15907.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15919.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15937.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15971.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15982.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15990.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst15997.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16003.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16006.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16011.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16015.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16061.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16090.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16107.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16110.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16121.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16139.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16144.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16145.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16149.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16154.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16164.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16180.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16239.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16275.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16286.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16294.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16316.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16334.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16345.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16359.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16361.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16397.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16398.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16422.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16437.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16438.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16451.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16453.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16457.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16464.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16488.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16497.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16528.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16530.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16535.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16539.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16550.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16554.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16559.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16577.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16585.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16598.xdti_16f_9t_96_ckmux21.xmux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16639.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16653.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16661.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16665.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16674.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16675.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16721.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16724.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16736.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16737.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16742.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16743.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16764.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16777.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16781.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16782.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16785.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16789.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16790.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16825.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16829.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16845.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16866.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16877.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16884.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16898.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16900.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16911.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16926.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16947.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16948.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16960.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16961.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16963.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16964.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16971.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16977.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst16984.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17014.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17073.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17077.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17093.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17103.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17125.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17130.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17134.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17137.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17142.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17144.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17158.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17177.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17186.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17196.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17199.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17204.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17210.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17228.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17230.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17247.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17262.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17269.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17273.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17287.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17288.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17291.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17295.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17296.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17297.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17317.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17362.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17366.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17377.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17378.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17408.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17417.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17421.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17428.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17429.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17430.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17449.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17450.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17451.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17458.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17481.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17502.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17504.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17512.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17514.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17522.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17524.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17525.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17528.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17543.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17569.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17590.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17595.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17600.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17630.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17667.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17674.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17693.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17699.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17701.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17730.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17745.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17746.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17749.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17770.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17795.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17806.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17815.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17818.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17830.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17859.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17921.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17923.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17929.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17941.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17954.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17955.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17958.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17963.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17967.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17971.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst17993.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18009.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18010.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18018.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18021.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18027.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18062.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18078.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18083.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18087.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18092.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18106.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18114.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18131.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18193.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18206.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18214.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18220.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18231.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18252.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18270.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18275.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18294.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18298.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18304.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18318.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18347.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18351.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18352.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18354.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18356.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18369.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18376.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18401.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18415.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18416.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18426.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18447.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18451.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18477.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18480.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18502.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18505.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18516.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18537.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18545.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18550.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18556.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18569.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18576.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18578.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18596.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18618.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18622.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18665.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18668.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18674.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18676.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18682.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18692.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18696.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18720.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18721.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18731.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18733.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18762.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18769.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18783.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18793.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18804.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18806.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18817.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18823.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18826.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18833.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18849.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18857.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18864.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18866.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18877.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18881.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18906.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18960.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18980.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18981.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18988.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst18989.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19000.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19013.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19027.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19029.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19039.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19050.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19053.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19056.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19072.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19074.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19075.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19076.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19078.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19084.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19094.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19120.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19125.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19130.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19140.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19145.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19147.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19152.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19163.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19170.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19176.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19184.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19186.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19200.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19208.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19218.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19228.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19233.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19238.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19242.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19246.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19248.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19255.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19269.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19271.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19274.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19279.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19281.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19289.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19297.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19298.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19316.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19332.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19337.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19346.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19362.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19367.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19382.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19393.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19423.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19425.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19438.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19445.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19451.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19454.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19459.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19463.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19472.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19473.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19503.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19509.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19510.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19526.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19531.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19540.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19541.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19552.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19557.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19574.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19580.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19590.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19593.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19610.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19614.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19615.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19624.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19638.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19651.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19655.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19659.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19668.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19677.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19685.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19698.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19725.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19733.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19741.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19746.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19749.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19777.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19781.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19789.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19865.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19866.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19874.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19875.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19883.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19891.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19912.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19927.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19956.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19958.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19959.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst19985.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20019.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20040.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20057.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20076.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20102.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20133.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20141.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20157.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20165.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20172.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20221.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20231.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20256.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20262.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20271.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20288.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20295.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20300.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20305.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20309.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20347.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20349.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20350.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20351.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20352.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20363.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20365.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20368.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20382.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20396.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20399.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20414.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20417.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20425.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20426.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20428.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20448.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20454.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20459.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20463.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20465.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20472.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20478.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20479.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20519.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20525.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20550.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20588.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20604.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20627.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20631.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20633.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20637.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20638.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20646.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20656.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20659.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20666.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20676.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20678.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20680.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20686.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20717.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20723.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20725.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20732.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20735.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20750.xdti_16f_9t_96_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20764.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20772.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20775.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20780.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20830.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20838.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20844.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20845.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20853.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20855.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20862.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20873.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20874.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20880.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20890.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20912.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20924.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20936.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20942.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20944.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20949.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20961.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20971.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst20991.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21012.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21030.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21047.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21069.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21076.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21095.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21105.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21109.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21111.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21115.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21123.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21131.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21142.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21144.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21146.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21147.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21171.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21186.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21187.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21189.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21196.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21205.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21206.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21228.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21235.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21244.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21246.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21248.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21255.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21267.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21275.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21278.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21281.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21288.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21298.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21332.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21338.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21350.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21353.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21358.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21370.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21378.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21387.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21394.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21396.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21401.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21405.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21432.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21468.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21474.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21495.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21513.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21536.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21539.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21541.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21549.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21570.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21580.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21600.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21607.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21609.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21613.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21636.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21641.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21663.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21703.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21704.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21717.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21723.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21739.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21740.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21757.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21779.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21788.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21831.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21841.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21856.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21862.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21864.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21875.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21880.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21899.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21911.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21913.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21914.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21915.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21919.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21923.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21933.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21935.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21936.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21939.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21942.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21944.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21961.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21975.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21981.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst21989.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22034.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22043.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22061.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22081.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22088.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22089.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22100.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22113.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22116.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22127.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22136.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22140.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22175.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22183.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22188.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22210.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22222.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22226.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22227.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22239.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22293.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22299.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22308.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22322.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22326.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22327.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22342.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22352.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22393.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22395.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22397.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22404.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22409.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22419.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22420.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22421.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22426.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22436.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22460.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22467.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22474.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22485.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22491.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22516.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22529.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22547.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22556.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22587.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22591.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22594.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22608.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22615.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22624.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22630.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22656.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22665.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22667.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22668.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22719.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22736.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22744.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22749.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22751.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22754.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22770.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22783.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22784.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22815.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22823.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22824.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22844.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22855.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22877.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22899.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22903.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22907.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22912.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22923.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22930.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22938.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22956.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22957.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22967.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22970.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22980.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22987.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst22989.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23006.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23009.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23010.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23015.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23020.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23022.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23056.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23079.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23086.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23121.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23127.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23137.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23139.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23142.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23151.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23190.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23193.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23195.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23215.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23221.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23232.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23243.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23266.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23276.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23277.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23294.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23324.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23344.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23352.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23356.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23359.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23368.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23371.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23372.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23374.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23377.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23415.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23418.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23435.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23448.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23480.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23481.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23485.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23488.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23489.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23502.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23529.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23554.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23560.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23580.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23586.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23602.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23609.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23623.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23625.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23635.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23638.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23639.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23640.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23647.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23654.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23657.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23663.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23671.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23675.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23710.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23733.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23737.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23749.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23750.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23757.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23766.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23772.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23791.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23796.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23797.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23802.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23804.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23811.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23826.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23833.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23840.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23853.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23857.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23875.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23876.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23882.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23885.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23891.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23892.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23908.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23918.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23952.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23957.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23960.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23962.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23984.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23988.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst23998.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24008.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24022.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24049.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24085.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24088.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24103.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24108.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24115.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24129.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24139.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24141.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24194.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24208.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24214.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24221.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24244.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24258.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24273.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24277.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24296.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24309.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24313.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24319.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24373.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24386.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24392.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24405.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24408.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24418.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24443.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24455.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24469.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24483.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24498.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24507.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24519.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24521.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24522.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24523.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24530.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24546.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24554.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24557.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24576.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24577.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24578.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24599.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24617.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24625.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24640.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24652.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24658.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24677.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24689.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24722.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24729.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24730.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24749.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24754.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24763.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24764.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24779.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24784.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24803.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24847.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24849.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24878.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24885.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24886.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24890.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24907.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24910.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24912.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24936.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24946.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24962.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24985.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24995.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst24998.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25003.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25008.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25009.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25023.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25040.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25043.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25050.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25076.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25095.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25112.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25124.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25129.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25131.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25135.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25145.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25164.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25176.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25177.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25187.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25200.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25202.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25204.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25209.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25215.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25224.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25227.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25235.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25239.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25246.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25264.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25266.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25310.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25316.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25329.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25331.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25333.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25337.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25342.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25356.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25365.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25366.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25368.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25378.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25387.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25404.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25405.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25410.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25417.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25432.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25454.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25457.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25474.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25522.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25529.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25534.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25542.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25557.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25558.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25570.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25591.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25624.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25625.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25639.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25676.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25695.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25702.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25706.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25718.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25719.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25723.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25729.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25759.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25780.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25811.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25812.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25823.xdti_16f_9t_96_mux21 41.67 50.00 25.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25833.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25836.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25841.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25842.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25851.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25855.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25867.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25874.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25877.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25888.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25891.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25920.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25924.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25925.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25956.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25963.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25972.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst25981.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26032.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26036.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26051.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26060.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26087.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26088.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26091.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26102.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26108.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26133.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26144.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26169.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26171.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26173.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26180.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26196.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26217.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26222.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26225.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26240.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26270.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26279.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26285.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26289.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26290.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26295.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26300.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26302.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26307.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26311.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26317.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26336.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26339.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26345.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26347.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26351.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26357.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26361.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26366.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26394.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26403.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26408.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26412.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26414.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26447.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26448.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26461.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26464.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26489.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26510.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26514.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26515.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26517.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26525.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26527.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26533.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26538.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26543.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26549.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26561.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26581.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26598.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26604.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26620.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26625.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26631.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26651.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26666.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26667.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26675.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26683.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26715.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26722.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26734.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26750.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26751.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26756.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26759.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26766.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26793.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26797.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26810.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26817.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26826.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26850.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26854.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26873.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26896.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26904.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26909.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26915.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26950.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26966.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26970.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26980.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26986.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26987.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26995.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst26997.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27010.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27024.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27037.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27050.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27064.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27072.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27104.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27113.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27114.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27115.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27144.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27149.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27174.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27176.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27179.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27197.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27199.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27203.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27205.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27218.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27246.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27281.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27293.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27308.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27331.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27351.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27358.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27364.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27386.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27404.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27407.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27413.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27432.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27456.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27457.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27460.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27482.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27516.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27517.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27523.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27524.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27547.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27554.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27559.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27587.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27588.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27605.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27608.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27612.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27631.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27634.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27642.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27663.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27665.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27679.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27697.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27715.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27751.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27753.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27764.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27780.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27798.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27813.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27817.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27819.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27828.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27849.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27898.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27901.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27905.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27908.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27914.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27929.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27930.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27934.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27935.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27959.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27975.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27979.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst27983.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28003.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28007.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28014.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28021.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28029.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28047.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28092.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28124.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28129.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28133.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28141.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28142.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28164.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28169.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28179.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28187.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28188.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28207.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28212.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28226.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28244.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28249.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28274.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28284.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28298.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28331.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28351.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28392.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28394.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28398.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28403.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28410.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28428.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28443.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28456.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28463.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28469.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28472.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28475.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28503.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28506.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28518.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28527.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28537.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28540.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28580.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28586.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28590.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28602.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28613.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28618.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28633.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28639.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28655.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28663.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28678.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28683.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28723.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28729.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28738.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28748.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28762.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28765.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28766.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28773.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28777.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28783.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28784.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28792.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28798.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28802.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28839.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28842.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28864.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28865.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28928.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28971.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28972.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28985.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst28990.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29005.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29007.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29017.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29048.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29069.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29070.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29076.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29084.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29086.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29109.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29124.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29143.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29151.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29183.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29199.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29219.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29225.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29239.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29245.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29252.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29261.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29267.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29274.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29275.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29282.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29299.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29306.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29315.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29327.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29336.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29342.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29346.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29357.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29367.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29376.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29391.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29392.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29399.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29408.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29411.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29424.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29468.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29471.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29476.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29488.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29492.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29522.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29526.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29530.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29550.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29551.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29565.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29597.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29599.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29632.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29637.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29643.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29648.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29651.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29654.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29659.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29674.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29689.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29731.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29749.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29763.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29766.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29801.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29839.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29850.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29875.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29878.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29880.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29889.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29920.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29940.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29963.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29964.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29968.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst29971.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30012.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30022.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30037.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30069.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30070.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30073.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30084.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30088.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30090.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30105.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30127.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30128.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30129.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30157.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30165.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30173.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30208.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30252.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30275.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30300.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30305.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30309.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30311.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30332.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30341.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30350.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30363.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30367.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30383.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30386.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30389.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30390.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30401.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30420.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30424.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30426.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30432.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30441.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30457.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30474.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30490.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30493.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30502.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30508.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30515.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30520.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30523.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30537.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30540.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30548.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30576.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30577.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30583.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30584.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30588.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30605.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30642.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30667.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30679.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30692.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30695.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30728.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30744.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30749.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30795.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30832.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30836.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30854.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30863.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30883.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30903.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30924.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30930.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4_18d_ctl30s2ckr2_jm.xinst30934.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst23.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst25.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst26.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst27.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst30.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst60.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst77.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst85.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst91.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst98.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst100.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst104.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst106.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst113.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst128.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst130.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst144.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst145.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst149.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst154.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst162.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst167.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst176.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst192.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst194.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst200.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst202.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst205.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst211.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst232.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst233.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst246.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst273.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst277.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst284.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst294.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst313.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst315.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst329.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst370.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst376.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst389.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst390.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst405.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst415.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst438.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst443.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst451.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst468.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst475.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst482.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst488.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst503.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst514.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst523.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst529.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst533.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst543.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst552.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst561.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst564.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst567.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst574.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst582.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst594.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst607.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst609.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst613.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst620.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst624.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst655.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst661.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst669.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst677.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst685.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst690.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst727.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst730.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst733.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst736.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst770.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst771.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst777.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst786.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst788.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst799.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst806.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst814.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst822.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst827.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst833.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst841.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst877.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst879.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst892.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst915.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst929.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst930.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst936.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst963.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst970.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst975.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst976.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst977.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst978.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1004.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1005.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1006.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1026.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1029.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1039.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1041.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1054.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1068.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1119.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1122.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1135.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1159.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1160.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1178.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1188.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1200.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1201.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1207.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1239.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1240.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1243.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1249.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1261.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1270.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1279.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1282.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1284.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1292.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1294.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1297.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1361.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1363.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1366.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1392.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1394.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1414.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1418.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1445.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1448.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1464.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1483.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1490.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1494.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1517.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1522.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1554.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1565.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1576.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1581.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1591.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1620.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1625.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1629.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1630.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1657.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1663.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1672.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1676.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1696.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1701.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1705.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1713.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1726.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1727.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1750.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1753.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1756.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1757.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1764.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1768.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1777.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1779.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1788.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1794.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1812.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1839.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1846.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1852.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1859.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1869.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1876.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1879.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1886.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1912.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1925.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1939.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1960.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1964.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst1971.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2005.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2011.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2017.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2021.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2024.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2026.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2043.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2045.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2052.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2059.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2064.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2084.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2086.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2095.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2097.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2105.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2113.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2115.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2123.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2125.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2127.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2130.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2146.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2155.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2167.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2177.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2181.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2183.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2194.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2201.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2202.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2215.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2232.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2234.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2240.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2243.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2247.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2264.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2277.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2284.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2285.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2286.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2290.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2322.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2323.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2326.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2342.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2343.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2372.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2388.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2403.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2404.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2413.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2423.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2426.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2431.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2436.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2487.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2488.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2496.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2509.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2526.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2551.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2555.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2567.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2601.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2606.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2626.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2628.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2635.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2639.xdti_16f_9t_96_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2644.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2647.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2673.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2674.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2691.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2707.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2709.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2719.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2726.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2728.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2737.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2750.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2753.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2760.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2768.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2790.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2796.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2798.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2803.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2837.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2840.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2841.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2848.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2864.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2869.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2878.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2883.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2891.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2908.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2922.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2924.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2928.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2933.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2945.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2951.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2957.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst2983.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3007.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3013.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3016.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3035.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3049.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3062.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3071.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3073.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3109.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3111.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3120.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3123.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3161.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3175.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3181.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3187.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3192.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3197.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3235.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3236.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3260.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3263.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3273.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3284.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3287.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3297.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3323.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3345.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3358.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3371.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3374.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3381.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3382.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3389.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3393.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3399.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3421.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3447.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3448.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3450.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3451.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3452.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3456.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3477.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3485.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3497.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3498.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3505.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3511.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3530.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3532.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3533.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3543.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3561.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3563.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3585.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3597.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3604.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3605.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3613.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3616.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3617.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3670.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3679.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3687.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3689.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3697.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3721.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3728.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3733.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3747.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3755.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3760.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3761.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3801.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3805.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3809.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3814.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3822.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3830.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3852.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3858.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3871.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3873.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3887.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3888.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3897.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3898.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3903.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3919.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3942.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3946.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3962.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3964.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3993.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3995.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst3996.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4001.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4003.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4007.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4012.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4013.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4026.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4030.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4040.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4052.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4054.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4059.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4077.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4097.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4111.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4116.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4135.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4196.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4198.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4217.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4218.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4265.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4291.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4308.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4316.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4326.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4342.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4349.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4356.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4360.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4399.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4403.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4409.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4413.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4435.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4452.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4456.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4461.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4465.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4489.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4491.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4504.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4533.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4558.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4562.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4579.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4593.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4594.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4606.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4608.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4620.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4624.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4626.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4630.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4631.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4639.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4658.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4667.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4671.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4676.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4677.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4691.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4697.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4712.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4721.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4727.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4733.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4744.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4747.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4749.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4759.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4769.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4781.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4788.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4796.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4798.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4820.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4821.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4823.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4861.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4882.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4895.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4904.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4916.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4928.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4930.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4944.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4948.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4949.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4953.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4971.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4973.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst4996.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5001.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5003.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5028.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5053.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5059.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5064.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5074.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5080.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5088.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5093.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5108.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5110.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5127.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5147.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5148.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5164.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5178.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5192.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5197.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5208.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5227.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5228.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5247.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5248.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5253.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5283.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5290.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5293.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5302.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5320.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5323.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5329.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5333.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5341.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5363.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5380.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5384.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5387.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5388.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5398.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5401.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5412.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5424.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5426.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5427.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5433.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5453.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5456.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5458.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5460.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5472.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5481.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5500.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5505.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5513.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5522.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5524.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5530.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5537.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5573.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5576.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5579.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5600.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5603.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5606.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5627.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5635.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5639.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5663.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5672.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5677.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5685.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5692.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5719.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5726.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5742.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5779.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5781.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5782.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5797.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5813.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5818.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5835.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5837.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5887.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5895.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5908.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5919.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5933.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5948.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5951.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5953.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5958.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5977.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5981.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5989.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5993.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5996.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst5997.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6031.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6068.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6092.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6094.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6098.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6110.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6113.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6119.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6121.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6123.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6136.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6143.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6146.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6163.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6183.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6192.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6193.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6195.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6197.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6199.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6215.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6235.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6254.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6260.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6261.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6262.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6263.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6275.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6287.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6312.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6314.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6319.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6321.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6341.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6348.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6361.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6368.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6373.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6377.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6384.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6397.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6404.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6407.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6418.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6420.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6439.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6454.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6455.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6488.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6490.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6506.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6512.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6535.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6549.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6561.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6563.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6579.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6588.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6591.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6595.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6603.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6606.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6619.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6624.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6632.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6633.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6658.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6661.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6668.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6679.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6692.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6696.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6716.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6723.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6724.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6734.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6740.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6752.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6758.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6778.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6792.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6799.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6800.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6801.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6803.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6806.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6864.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6880.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6883.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6905.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6907.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6935.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6941.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6947.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6948.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6956.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6965.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6974.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6977.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst6982.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7017.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7032.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7064.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7081.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7082.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7083.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7085.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7087.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7095.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7102.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7127.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7144.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7148.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7153.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7157.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7159.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7161.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7168.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7180.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7197.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7208.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7230.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7238.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7255.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7256.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7302.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7317.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7319.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7329.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7352.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7355.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7358.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7366.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7367.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7374.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7376.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7389.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7392.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7394.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7395.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7400.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7406.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7416.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7424.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7433.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7436.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7447.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7448.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7450.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7460.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7462.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7471.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7475.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7514.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7539.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7564.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7565.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7577.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7603.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7614.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7648.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7674.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7677.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7683.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7687.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7689.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7700.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7704.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7716.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7717.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7719.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7721.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7744.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7751.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7765.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7766.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7769.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7774.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7807.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7829.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7838.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7858.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7861.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7874.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7893.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7898.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7903.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7910.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7921.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7923.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7925.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7930.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7943.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7967.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7973.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7991.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst7995.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8003.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8004.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8024.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8025.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8028.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8029.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8058.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8070.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8089.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8097.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8104.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8107.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8116.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8119.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8121.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8122.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8124.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8125.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8157.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8173.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8174.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8199.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8208.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8214.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8215.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8224.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8232.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8263.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8274.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8277.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8278.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8282.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8284.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8297.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8303.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8307.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8312.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8313.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8327.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8349.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8358.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8368.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8379.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8380.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8386.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8394.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8419.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8443.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8444.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8456.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8463.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8474.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8491.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8497.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8501.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8537.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8542.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8546.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8553.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8558.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8576.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8590.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8611.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8628.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8639.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8642.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8649.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8651.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8654.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8662.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8681.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8690.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8718.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8725.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8757.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8762.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8775.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8780.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8781.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8788.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8807.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8833.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8857.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8871.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8885.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8887.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8889.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8892.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8937.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8949.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8950.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8956.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst8972.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9002.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9015.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9026.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9041.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9055.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9060.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9071.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9092.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9093.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9096.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9102.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9112.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9131.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9142.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9143.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9147.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9158.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9159.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9170.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9174.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9206.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9210.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9229.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9238.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9239.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9246.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9253.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9255.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9256.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9257.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9264.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9267.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9274.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9276.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9280.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9284.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9287.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9301.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9319.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9331.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9332.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9363.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9364.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9366.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9369.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9383.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9400.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9411.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9416.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9456.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9466.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9475.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9478.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9481.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9487.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9499.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9522.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9523.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9524.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9529.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9534.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9544.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9582.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9589.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9615.xdti_16f_9t_96_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9639.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9665.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9670.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9673.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9674.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9690.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9691.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9693.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9725.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9738.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9756.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9759.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9760.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9768.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9777.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9779.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9785.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9790.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9794.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9797.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9826.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9835.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9836.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9871.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9883.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9913.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9937.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9941.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9947.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9978.xdti_16f_9t_96_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst9991.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10001.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10007.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10012.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10023.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10029.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10036.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10037.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10039.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10061.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10064.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10081.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10083.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10095.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10109.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10116.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10143.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10144.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10157.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10174.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10203.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10213.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10214.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10222.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10223.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10257.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10277.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10286.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10290.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10300.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10311.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10315.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10358.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10359.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10378.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10383.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10386.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10391.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10394.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10399.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10401.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10408.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10416.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10419.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10430.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10466.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10468.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10472.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10479.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10485.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10495.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10498.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10502.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10511.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10514.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10520.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10523.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10525.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10532.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10541.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10543.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10551.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10553.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10569.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10591.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10597.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10604.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10610.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10619.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10628.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10632.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10645.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10646.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10650.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10657.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10686.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10687.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10693.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10696.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10697.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10710.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10729.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10738.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10745.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10748.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10752.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10755.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10776.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10782.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10796.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10802.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10810.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10827.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10839.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10873.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10899.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10923.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10927.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10977.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10982.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst10998.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11022.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11023.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11024.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11033.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11036.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11045.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11057.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11072.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11088.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11104.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11119.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11124.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11164.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11168.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11171.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11187.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11189.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11209.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11211.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11222.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11239.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11253.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11278.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11304.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11307.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11313.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11334.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11349.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11352.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11359.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11361.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11364.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11387.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11398.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11407.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11412.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11426.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11457.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11465.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11490.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11491.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11499.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11503.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11506.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11521.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11535.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11548.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11553.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11588.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11589.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11604.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11624.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11626.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11630.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11643.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11647.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11656.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11659.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11664.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11667.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11676.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11682.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11699.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11707.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11738.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11739.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11744.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11779.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11780.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11785.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11801.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11807.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11838.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11848.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11856.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11884.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11894.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11905.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11906.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11909.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11932.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11933.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11941.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11944.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11945.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11954.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11977.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11978.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11986.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11994.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst11995.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12011.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12054.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12056.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12082.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12089.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12099.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12124.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12132.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12140.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12141.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12174.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12183.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12216.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12223.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12228.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12229.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12242.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12243.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12261.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12268.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12284.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12285.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12286.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12288.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12292.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12308.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12310.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12311.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12329.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12344.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12351.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12368.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12377.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12395.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12411.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12416.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12424.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12432.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12433.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12444.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12445.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12460.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12480.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12494.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12496.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12527.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12529.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12545.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12548.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12557.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12574.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12586.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12593.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12595.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12606.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12609.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12619.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12629.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12631.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12642.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12644.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12645.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12649.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12650.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12651.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12659.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12686.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12698.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12705.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12727.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12733.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12741.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12744.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12766.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[0].xinst12777.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst23.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst25.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst26.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst27.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst30.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst60.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst77.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst85.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst91.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst98.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst100.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst104.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst106.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst113.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst128.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst130.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst144.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst145.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst149.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst154.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst162.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst167.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst176.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst192.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst194.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst200.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst202.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst205.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst211.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst232.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst233.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst246.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst273.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst277.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst284.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst294.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst313.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst315.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst329.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst370.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst376.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst389.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst390.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst405.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst415.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst438.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst443.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst451.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst468.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst475.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst482.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst488.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst503.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst514.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst523.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst529.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst533.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst543.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst552.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst561.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst564.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst567.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst574.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst582.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst594.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst607.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst609.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst613.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst620.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst624.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst655.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst661.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst669.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst677.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst685.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst690.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst727.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst730.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst733.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst736.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst770.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst771.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst777.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst786.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst788.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst799.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst806.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst814.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst822.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst827.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst833.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst841.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst877.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst879.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst892.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst915.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst929.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst930.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst936.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst963.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst970.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst975.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst976.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst977.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst978.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1004.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1005.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1006.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1026.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1029.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1039.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1041.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1054.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1068.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1119.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1122.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1135.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1159.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1160.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1178.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1188.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1200.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1201.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1207.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1239.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1240.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1243.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1249.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1261.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1270.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1279.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1282.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1284.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1292.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1294.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1297.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1361.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1363.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1366.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1392.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1394.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1414.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1418.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1445.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1448.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1464.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1483.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1490.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1494.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1517.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1522.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1554.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1565.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1576.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1581.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1591.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1620.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1625.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1629.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1630.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1657.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1663.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1672.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1676.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1696.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1701.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1705.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1713.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1726.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1727.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1750.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1753.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1756.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1757.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1764.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1768.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1777.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1779.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1788.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1794.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1812.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1839.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1846.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1852.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1859.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1869.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1876.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1879.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1886.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1912.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1925.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1939.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1960.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1964.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst1971.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2005.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2011.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2017.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2021.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2024.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2026.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2043.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2045.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2052.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2059.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2064.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2084.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2086.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2095.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2097.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2105.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2113.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2115.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2123.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2125.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2127.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2130.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2146.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2155.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2167.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2177.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2181.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2183.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2194.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2201.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2202.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2215.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2232.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2234.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2240.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2243.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2247.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2264.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2277.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2284.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2285.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2286.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2290.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2322.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2323.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2326.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2342.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2343.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2372.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2388.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2403.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2404.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2413.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2423.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2426.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2431.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2436.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2487.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2488.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2496.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2509.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2526.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2551.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2555.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2567.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2601.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2606.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2626.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2628.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2635.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2639.xdti_16f_9t_96_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2644.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2647.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2673.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2674.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2691.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2707.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2709.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2719.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2726.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2728.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2737.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2750.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2753.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2760.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2768.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2790.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2796.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2798.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2803.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2837.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2840.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2841.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2848.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2864.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2869.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2878.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2883.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2891.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2908.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2922.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2924.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2928.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2933.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2945.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2951.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2957.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst2983.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3007.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3013.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3016.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3035.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3049.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3062.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3071.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3073.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3109.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3111.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3120.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3123.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3161.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3175.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3181.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3187.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3192.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3197.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3235.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3236.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3260.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3263.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3273.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3284.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3287.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3297.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3323.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3345.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3358.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3371.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3374.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3381.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3382.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3389.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3393.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3399.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3421.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3447.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3448.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3450.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3451.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3452.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3456.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3477.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3485.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3497.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3498.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3505.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3511.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3530.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3532.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3533.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3543.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3561.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3563.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3585.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3597.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3604.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3605.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3613.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3616.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3617.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3670.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3679.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3687.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3689.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3697.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3721.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3728.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3733.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3747.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3755.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3760.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3761.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3801.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3805.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3809.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3814.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3822.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3830.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3852.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3858.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3871.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3873.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3887.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3888.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3897.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3898.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3903.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3919.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3942.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3946.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3962.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3964.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3993.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3995.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst3996.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4001.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4003.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4007.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4012.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4013.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4026.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4030.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4040.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4052.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4054.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4059.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4077.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4097.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4111.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4116.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4135.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4196.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4198.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4217.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4218.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4265.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4291.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4308.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4316.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4326.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4342.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4349.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4356.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4360.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4399.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4403.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4409.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4413.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4435.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4452.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4456.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4461.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4465.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4489.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4491.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4504.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4533.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4558.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4562.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4579.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4593.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4594.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4606.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4608.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4620.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4624.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4626.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4630.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4631.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4639.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4658.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4667.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4671.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4676.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4677.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4691.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4697.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4712.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4721.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4727.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4733.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4744.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4747.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4749.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4759.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4769.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4781.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4788.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4796.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4798.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4820.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4821.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4823.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4861.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4882.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4895.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4904.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4916.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4928.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4930.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4944.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4948.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4949.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4953.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4971.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4973.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst4996.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5001.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5003.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5028.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5053.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5059.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5064.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5074.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5080.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5088.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5093.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5108.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5110.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5127.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5147.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5148.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5164.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5178.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5192.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5197.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5208.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5227.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5228.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5247.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5248.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5253.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5283.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5290.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5293.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5302.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5320.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5323.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5329.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5333.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5341.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5363.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5380.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5384.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5387.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5388.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5398.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5401.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5412.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5424.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5426.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5427.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5433.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5453.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5456.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5458.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5460.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5472.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5481.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5500.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5505.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5513.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5522.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5524.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5530.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5537.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5573.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5576.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5579.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5600.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5603.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5606.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5627.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5635.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5639.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5663.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5672.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5677.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5685.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5692.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5719.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5726.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5742.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5779.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5781.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5782.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5797.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5813.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5818.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5835.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5837.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5887.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5895.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5908.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5919.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5933.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5948.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5951.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5953.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5958.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5977.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5981.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5989.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5993.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5996.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst5997.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6031.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6068.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6092.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6094.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6098.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6110.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6113.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6119.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6121.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6123.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6136.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6143.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6146.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6163.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6183.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6192.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6193.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6195.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6197.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6199.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6215.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6235.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6254.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6260.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6261.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6262.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6263.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6275.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6287.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6312.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6314.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6319.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6321.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6341.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6348.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6361.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6368.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6373.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6377.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6384.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6397.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6404.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6407.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6418.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6420.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6439.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6454.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6455.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6488.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6490.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6506.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6512.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6535.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6549.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6561.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6563.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6579.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6588.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6591.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6595.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6603.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6606.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6619.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6624.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6632.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6633.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6658.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6661.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6668.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6679.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6692.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6696.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6716.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6723.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6724.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6734.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6740.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6752.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6758.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6778.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6792.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6799.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6800.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6801.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6803.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6806.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6864.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6880.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6883.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6905.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6907.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6935.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6941.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6947.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6948.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6956.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6965.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6974.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6977.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst6982.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7017.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7032.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7064.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7081.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7082.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7083.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7085.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7087.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7095.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7102.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7127.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7144.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7148.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7153.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7157.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7159.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7161.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7168.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7180.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7197.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7208.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7230.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7238.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7255.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7256.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7302.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7317.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7319.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7329.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7352.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7355.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7358.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7366.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7367.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7374.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7376.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7389.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7392.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7394.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7395.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7400.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7406.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7416.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7424.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7433.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7436.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7447.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7448.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7450.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7460.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7462.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7471.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7475.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7514.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7539.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7564.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7565.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7577.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7603.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7614.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7648.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7674.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7677.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7683.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7687.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7689.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7700.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7704.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7716.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7717.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7719.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7721.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7744.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7751.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7765.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7766.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7769.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7774.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7807.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7829.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7838.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7858.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7861.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7874.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7893.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7898.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7903.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7910.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7921.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7923.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7925.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7930.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7943.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7967.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7973.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7991.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst7995.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8003.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8004.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8024.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8025.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8028.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8029.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8058.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8070.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8089.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8097.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8104.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8107.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8116.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8119.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8121.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8122.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8124.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8125.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8157.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8173.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8174.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8199.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8208.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8214.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8215.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8224.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8232.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8263.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8274.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8277.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8278.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8282.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8284.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8297.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8303.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8307.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8312.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8313.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8327.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8349.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8358.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8368.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8379.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8380.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8386.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8394.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8419.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8443.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8444.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8456.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8463.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8474.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8491.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8497.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8501.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8537.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8542.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8546.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8553.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8558.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8576.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8590.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8611.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8628.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8639.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8642.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8649.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8651.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8654.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8662.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8681.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8690.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8718.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8725.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8757.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8762.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8775.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8780.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8781.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8788.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8807.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8833.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8857.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8871.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8885.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8887.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8889.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8892.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8937.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8949.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8950.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8956.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst8972.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9002.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9015.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9026.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9041.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9055.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9060.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9071.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9092.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9093.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9096.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9102.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9112.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9131.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9142.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9143.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9147.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9158.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9159.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9170.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9174.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9206.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9210.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9229.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9238.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9239.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9246.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9253.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9255.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9256.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9257.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9264.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9267.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9274.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9276.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9280.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9284.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9287.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9301.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9319.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9331.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9332.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9363.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9364.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9366.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9369.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9383.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9400.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9411.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9416.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9456.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9466.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9475.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9478.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9481.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9487.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9499.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9522.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9523.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9524.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9529.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9534.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9544.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9582.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9589.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9615.xdti_16f_9t_96_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9639.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9665.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9670.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9673.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9674.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9690.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9691.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9693.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9725.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9738.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9756.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9759.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9760.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9768.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9777.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9779.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9785.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9790.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9794.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9797.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9826.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9835.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9836.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9871.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9883.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9913.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9937.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9941.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9947.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9978.xdti_16f_9t_96_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst9991.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10001.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10007.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10012.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10023.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10029.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10036.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10037.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10039.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10061.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10064.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10081.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10083.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10095.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10109.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10116.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10143.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10144.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10157.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10174.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10203.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10213.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10214.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10222.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10223.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10257.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10277.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10286.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10290.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10300.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10311.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10315.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10358.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10359.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10378.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10383.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10386.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10391.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10394.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10399.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10401.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10408.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10416.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10419.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10430.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10466.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10468.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10472.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10479.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10485.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10495.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10498.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10502.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10511.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10514.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10520.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10523.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10525.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10532.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10541.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10543.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10551.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10553.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10569.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10591.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10597.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10604.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10610.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10619.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10628.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10632.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10645.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10646.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10650.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10657.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10686.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10687.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10693.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10696.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10697.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10710.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10729.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10738.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10745.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10748.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10752.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10755.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10776.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10782.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10796.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10802.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10810.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10827.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10839.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10873.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10899.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10923.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10927.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10977.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10982.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst10998.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11022.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11023.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11024.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11033.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11036.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11045.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11057.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11072.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11088.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11104.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11119.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11124.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11164.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11168.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11171.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11187.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11189.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11209.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11211.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11222.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11239.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11253.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11278.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11304.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11307.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11313.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11334.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11349.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11352.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11359.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11361.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11364.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11387.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11398.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11407.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11412.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11426.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11457.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11465.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11490.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11491.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11499.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11503.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11506.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11521.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11535.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11548.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11553.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11588.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11589.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11604.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11624.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11626.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11630.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11643.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11647.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11656.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11659.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11664.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11667.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11676.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11682.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11699.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11707.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11738.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11739.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11744.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11779.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11780.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11785.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11801.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11807.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11838.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11848.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11856.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11884.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11894.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11905.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11906.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11909.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11932.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11933.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11941.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11944.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11945.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11954.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11977.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11978.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11986.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11994.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst11995.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12011.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12054.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12056.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12082.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12089.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12099.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12124.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12132.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12140.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12141.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12174.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12183.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12216.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12223.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12228.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12229.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12242.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12243.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12261.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12268.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12284.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12285.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12286.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12288.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12292.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12308.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12310.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12311.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12329.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12344.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12351.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12368.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12377.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12395.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12411.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12416.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12424.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12432.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12433.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12444.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12445.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12460.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12480.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12494.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12496.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12527.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12529.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12545.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12548.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12557.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12574.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12586.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12593.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12595.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12606.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12609.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12619.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12629.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12631.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12642.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12644.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12645.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12649.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12650.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12651.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12659.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12686.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12698.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12705.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12727.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12733.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12741.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12744.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12766.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[1].xinst12777.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst23.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst25.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst26.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst27.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst30.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst60.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst77.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst85.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst91.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst98.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst100.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst104.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst106.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst113.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst128.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst130.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst144.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst145.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst149.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst154.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst162.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst167.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst176.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst192.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst194.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst200.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst202.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst205.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst211.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst232.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst233.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst246.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst273.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst277.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst284.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst294.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst313.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst315.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst329.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst370.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst376.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst389.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst390.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst405.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst415.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst438.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst443.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst451.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst468.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst475.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst482.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst488.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst503.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst514.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst523.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst529.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst533.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst543.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst552.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst561.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst564.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst567.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst574.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst582.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst594.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst607.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst609.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst613.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst620.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst624.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst655.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst661.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst669.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst677.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst685.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst690.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst727.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst730.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst733.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst736.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst770.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst771.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst777.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst786.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst788.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst799.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst806.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst814.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst822.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst827.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst833.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst841.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst877.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst879.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst892.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst915.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst929.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst930.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst936.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst963.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst970.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst975.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst976.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst977.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst978.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1004.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1005.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1006.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1026.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1029.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1039.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1041.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1054.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1068.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1119.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1122.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1135.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1159.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1160.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1178.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1188.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1200.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1201.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1207.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1239.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1240.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1243.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1249.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1261.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1270.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1279.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1282.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1284.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1292.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1294.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1297.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1361.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1363.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1366.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1392.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1394.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1414.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1418.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1445.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1448.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1464.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1483.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1490.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1494.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1517.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1522.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1554.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1565.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1576.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1581.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1591.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1620.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1625.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1629.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1630.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1657.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1663.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1672.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1676.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1696.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1701.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1705.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1713.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1726.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1727.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1750.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1753.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1756.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1757.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1764.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1768.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1777.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1779.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1788.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1794.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1812.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1839.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1846.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1852.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1859.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1869.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1876.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1879.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1886.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1912.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1925.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1939.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1960.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1964.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst1971.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2005.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2011.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2017.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2021.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2024.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2026.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2043.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2045.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2052.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2059.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2064.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2084.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2086.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2095.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2097.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2105.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2113.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2115.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2123.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2125.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2127.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2130.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2146.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2155.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2167.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2177.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2181.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2183.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2194.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2201.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2202.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2215.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2232.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2234.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2240.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2243.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2247.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2264.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2277.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2284.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2285.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2286.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2290.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2322.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2323.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2326.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2342.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2343.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2372.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2388.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2403.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2404.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2413.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2423.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2426.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2431.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2436.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2487.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2488.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2496.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2509.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2526.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2551.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2555.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2567.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2601.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2606.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2626.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2628.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2635.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2639.xdti_16f_9t_96_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2644.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2647.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2673.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2674.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2691.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2707.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2709.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2719.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2726.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2728.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2737.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2750.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2753.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2760.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2768.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2790.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2796.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2798.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2803.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2837.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2840.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2841.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2848.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2864.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2869.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2878.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2883.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2891.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2908.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2922.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2924.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2928.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2933.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2945.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2951.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2957.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst2983.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3007.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3013.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3016.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3035.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3049.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3062.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3071.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3073.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3109.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3111.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3120.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3123.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3161.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3175.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3181.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3187.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3192.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3197.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3235.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3236.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3260.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3263.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3273.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3284.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3287.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3297.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3323.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3345.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3358.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3371.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3374.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3381.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3382.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3389.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3393.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3399.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3421.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3447.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3448.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3450.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3451.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3452.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3456.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3477.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3485.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3497.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3498.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3505.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3511.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3530.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3532.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3533.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3543.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3561.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3563.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3585.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3597.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3604.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3605.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3613.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3616.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3617.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3670.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3679.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3687.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3689.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3697.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3721.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3728.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3733.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3747.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3755.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3760.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3761.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3801.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3805.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3809.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3814.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3822.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3830.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3852.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3858.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3871.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3873.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3887.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3888.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3897.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3898.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3903.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3919.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3942.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3946.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3962.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3964.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3993.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3995.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst3996.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4001.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4003.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4007.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4012.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4013.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4026.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4030.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4040.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4052.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4054.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4059.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4077.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4097.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4111.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4116.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4135.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4196.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4198.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4217.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4218.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4265.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4291.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4308.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4316.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4326.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4342.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4349.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4356.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4360.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4399.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4403.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4409.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4413.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4435.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4452.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4456.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4461.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4465.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4489.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4491.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4504.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4533.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4558.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4562.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4579.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4593.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4594.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4606.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4608.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4620.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4624.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4626.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4630.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4631.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4639.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4658.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4667.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4671.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4676.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4677.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4691.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4697.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4712.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4721.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4727.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4733.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4744.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4747.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4749.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4759.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4769.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4781.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4788.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4796.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4798.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4820.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4821.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4823.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4861.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4882.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4895.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4904.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4916.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4928.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4930.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4944.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4948.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4949.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4953.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4971.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4973.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst4996.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5001.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5003.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5028.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5053.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5059.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5064.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5074.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5080.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5088.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5093.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5108.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5110.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5127.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5147.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5148.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5164.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5178.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5192.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5197.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5208.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5227.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5228.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5247.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5248.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5253.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5283.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5290.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5293.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5302.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5320.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5323.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5329.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5333.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5341.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5363.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5380.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5384.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5387.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5388.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5398.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5401.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5412.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5424.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5426.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5427.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5433.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5453.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5456.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5458.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5460.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5472.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5481.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5500.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5505.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5513.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5522.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5524.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5530.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5537.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5573.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5576.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5579.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5600.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5603.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5606.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5627.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5635.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5639.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5663.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5672.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5677.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5685.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5692.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5719.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5726.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5742.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5779.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5781.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5782.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5797.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5813.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5818.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5835.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5837.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5887.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5895.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5908.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5919.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5933.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5948.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5951.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5953.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5958.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5977.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5981.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5989.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5993.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5996.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst5997.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6031.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6068.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6092.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6094.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6098.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6110.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6113.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6119.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6121.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6123.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6136.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6143.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6146.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6163.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6183.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6192.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6193.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6195.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6197.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6199.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6215.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6235.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6254.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6260.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6261.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6262.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6263.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6275.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6287.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6312.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6314.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6319.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6321.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6341.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6348.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6361.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6368.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6373.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6377.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6384.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6397.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6404.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6407.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6418.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6420.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6439.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6454.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6455.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6488.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6490.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6506.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6512.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6535.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6549.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6561.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6563.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6579.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6588.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6591.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6595.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6603.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6606.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6619.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6624.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6632.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6633.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6658.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6661.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6668.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6679.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6692.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6696.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6716.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6723.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6724.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6734.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6740.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6752.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6758.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6778.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6792.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6799.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6800.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6801.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6803.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6806.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6864.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6880.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6883.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6905.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6907.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6935.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6941.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6947.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6948.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6956.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6965.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6974.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6977.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst6982.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7017.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7032.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7064.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7081.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7082.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7083.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7085.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7087.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7095.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7102.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7127.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7144.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7148.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7153.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7157.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7159.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7161.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7168.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7180.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7197.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7208.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7230.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7238.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7255.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7256.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7302.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7317.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7319.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7329.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7352.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7355.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7358.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7366.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7367.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7374.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7376.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7389.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7392.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7394.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7395.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7400.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7406.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7416.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7424.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7433.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7436.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7447.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7448.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7450.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7460.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7462.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7471.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7475.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7514.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7539.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7564.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7565.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7577.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7603.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7614.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7648.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7674.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7677.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7683.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7687.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7689.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7700.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7704.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7716.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7717.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7719.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7721.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7744.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7751.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7765.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7766.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7769.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7774.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7807.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7829.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7838.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7858.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7861.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7874.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7893.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7898.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7903.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7910.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7921.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7923.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7925.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7930.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7943.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7967.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7973.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7991.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst7995.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8003.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8004.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8024.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8025.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8028.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8029.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8058.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8070.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8089.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8097.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8104.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8107.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8116.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8119.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8121.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8122.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8124.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8125.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8157.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8173.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8174.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8199.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8208.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8214.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8215.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8224.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8232.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8263.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8274.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8277.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8278.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8282.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8284.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8297.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8303.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8307.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8312.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8313.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8327.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8349.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8358.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8368.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8379.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8380.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8386.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8394.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8419.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8443.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8444.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8456.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8463.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8474.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8491.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8497.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8501.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8537.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8542.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8546.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8553.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8558.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8576.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8590.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8611.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8628.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8639.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8642.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8649.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8651.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8654.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8662.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8681.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8690.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8718.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8725.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8757.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8762.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8775.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8780.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8781.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8788.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8807.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8833.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8857.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8871.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8885.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8887.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8889.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8892.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8937.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8949.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8950.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8956.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst8972.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9002.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9015.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9026.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9041.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9055.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9060.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9071.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9092.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9093.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9096.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9102.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9112.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9131.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9142.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9143.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9147.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9158.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9159.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9170.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9174.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9206.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9210.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9229.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9238.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9239.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9246.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9253.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9255.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9256.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9257.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9264.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9267.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9274.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9276.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9280.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9284.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9287.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9301.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9319.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9331.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9332.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9363.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9364.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9366.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9369.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9383.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9400.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9411.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9416.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9456.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9466.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9475.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9478.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9481.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9487.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9499.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9522.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9523.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9524.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9529.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9534.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9544.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9582.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9589.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9615.xdti_16f_9t_96_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9639.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9665.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9670.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9673.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9674.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9690.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9691.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9693.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9725.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9738.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9756.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9759.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9760.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9768.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9777.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9779.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9785.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9790.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9794.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9797.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9826.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9835.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9836.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9871.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9883.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9913.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9937.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9941.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9947.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9978.xdti_16f_9t_96_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst9991.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10001.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10007.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10012.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10023.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10029.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10036.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10037.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10039.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10061.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10064.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10081.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10083.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10095.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10109.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10116.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10143.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10144.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10157.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10174.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10203.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10213.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10214.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10222.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10223.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10257.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10277.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10286.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10290.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10300.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10311.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10315.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10358.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10359.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10378.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10383.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10386.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10391.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10394.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10399.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10401.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10408.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10416.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10419.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10430.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10466.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10468.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10472.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10479.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10485.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10495.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10498.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10502.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10511.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10514.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10520.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10523.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10525.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10532.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10541.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10543.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10551.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10553.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10569.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10591.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10597.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10604.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10610.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10619.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10628.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10632.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10645.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10646.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10650.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10657.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10686.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10687.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10693.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10696.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10697.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10710.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10729.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10738.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10745.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10748.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10752.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10755.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10776.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10782.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10796.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10802.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10810.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10827.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10839.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10873.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10899.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10923.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10927.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10977.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10982.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst10998.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11022.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11023.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11024.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11033.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11036.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11045.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11057.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11072.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11088.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11104.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11119.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11124.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11164.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11168.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11171.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11187.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11189.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11209.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11211.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11222.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11239.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11253.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11278.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11304.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11307.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11313.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11334.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11349.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11352.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11359.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11361.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11364.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11387.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11398.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11407.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11412.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11426.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11457.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11465.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11490.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11491.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11499.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11503.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11506.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11521.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11535.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11548.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11553.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11588.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11589.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11604.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11624.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11626.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11630.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11643.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11647.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11656.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11659.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11664.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11667.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11676.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11682.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11699.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11707.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11738.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11739.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11744.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11779.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11780.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11785.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11801.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11807.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11838.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11848.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11856.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11884.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11894.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11905.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11906.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11909.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11932.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11933.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11941.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11944.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11945.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11954.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11977.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11978.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11986.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11994.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst11995.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12011.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12054.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12056.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12082.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12089.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12099.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12124.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12132.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12140.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12141.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12174.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12183.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12216.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12223.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12228.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12229.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12242.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12243.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12261.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12268.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12284.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12285.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12286.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12288.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12292.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12308.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12310.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12311.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12329.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12344.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12351.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12368.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12377.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12395.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12411.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12416.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12424.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12432.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12433.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12444.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12445.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12460.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12480.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12494.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12496.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12527.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12529.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12545.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12548.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12557.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12574.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12586.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12593.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12595.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12606.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12609.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12619.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12629.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12631.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12642.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12644.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12645.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12649.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12650.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12651.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12659.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12686.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12698.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12705.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12727.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12733.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12741.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12744.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12766.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[2].xinst12777.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst23.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst25.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst26.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst27.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst30.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst60.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst77.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst85.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst91.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst98.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst100.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst104.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst106.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst113.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst128.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst130.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst144.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst145.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst149.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst154.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst162.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst167.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst176.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst192.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst194.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst200.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst202.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst205.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst211.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst232.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst233.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst246.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst273.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst277.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst284.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst294.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst313.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst315.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst329.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst370.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst376.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst389.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst390.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst405.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst415.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst438.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst443.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst451.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst468.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst475.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst482.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst488.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst503.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst514.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst523.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst529.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst533.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst543.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst552.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst561.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst564.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst567.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst574.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst582.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst594.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst607.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst609.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst613.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst620.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst624.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst655.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst661.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst669.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst677.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst685.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst690.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst727.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst730.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst733.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst736.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst770.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst771.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst777.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst786.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst788.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst799.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst806.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst814.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst822.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst827.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst833.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst841.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst877.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst879.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst892.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst915.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst929.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst930.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst936.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst963.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst970.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst975.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst976.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst977.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst978.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1004.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1005.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1006.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1026.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1029.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1039.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1041.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1054.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1068.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1119.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1122.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1135.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1159.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1160.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1178.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1188.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1200.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1201.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1207.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1239.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1240.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1243.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1249.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1261.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1270.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1279.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1282.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1284.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1292.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1294.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1297.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1361.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1363.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1366.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1392.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1394.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1414.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1418.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1445.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1448.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1464.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1483.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1490.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1494.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1517.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1522.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1554.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1565.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1576.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1581.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1591.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1620.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1625.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1629.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1630.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1657.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1663.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1672.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1676.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1696.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1701.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1705.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1713.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1726.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1727.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1750.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1753.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1756.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1757.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1764.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1768.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1777.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1779.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1788.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1794.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1812.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1839.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1846.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1852.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1859.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1869.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1876.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1879.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1886.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1912.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1925.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1939.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1960.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1964.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst1971.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2005.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2011.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2017.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2021.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2024.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2026.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2043.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2045.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2052.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2059.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2064.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2084.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2086.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2095.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2097.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2105.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2113.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2115.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2123.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2125.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2127.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2130.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2146.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2155.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2167.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2177.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2181.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2183.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2194.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2201.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2202.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2215.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2232.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2234.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2240.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2243.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2247.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2264.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2277.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2284.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2285.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2286.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2290.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2322.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2323.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2326.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2342.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2343.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2372.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2388.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2403.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2404.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2413.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2423.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2426.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2431.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2436.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2487.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2488.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2496.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2509.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2526.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2551.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2555.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2567.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2601.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2606.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2626.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2628.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2635.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2639.xdti_16f_9t_96_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2644.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2647.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2673.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2674.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2691.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2707.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2709.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2719.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2726.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2728.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2737.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2750.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2753.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2760.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2768.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2790.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2796.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2798.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2803.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2837.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2840.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2841.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2848.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2864.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2869.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2878.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2883.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2891.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2908.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2922.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2924.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2928.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2933.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2945.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2951.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2957.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst2983.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3007.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3013.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3016.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3035.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3049.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3062.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3071.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3073.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3109.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3111.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3120.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3123.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3161.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3175.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3181.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3187.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3192.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3197.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3235.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3236.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3260.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3263.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3273.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3284.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3287.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3297.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3323.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3345.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3358.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3371.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3374.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3381.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3382.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3389.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3393.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3399.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3421.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3447.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3448.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3450.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3451.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3452.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3456.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3477.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3485.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3497.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3498.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3505.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3511.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3530.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3532.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3533.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3543.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3561.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3563.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3585.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3597.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3604.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3605.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3613.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3616.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3617.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3670.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3679.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3687.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3689.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3697.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3721.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3728.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3733.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3747.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3755.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3760.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3761.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3801.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3805.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3809.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3814.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3822.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3830.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3852.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3858.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3871.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3873.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3887.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3888.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3897.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3898.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3903.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3919.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3942.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3946.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3962.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3964.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3993.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3995.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst3996.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4001.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4003.xdti_16f_9t_96_ckmux21.xmux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4007.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4012.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4013.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4026.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4030.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4040.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4052.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4054.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4059.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4077.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4097.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4111.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4116.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4135.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4196.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4198.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4217.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4218.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4265.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4291.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4308.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4316.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4326.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4342.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4349.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4356.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4360.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4399.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4403.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4409.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4413.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4435.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4452.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4456.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4461.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4465.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4489.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4491.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4504.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4533.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4558.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4562.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4579.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4593.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4594.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4606.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4608.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4620.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4624.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4626.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4630.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4631.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4639.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4658.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4667.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4671.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4676.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4677.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4691.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4697.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4712.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4721.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4727.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4733.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4744.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4747.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4749.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4759.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4769.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4781.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4788.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4796.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4798.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4820.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4821.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4823.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4861.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4882.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4895.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4904.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4916.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4928.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4930.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4944.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4948.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4949.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4953.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4971.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4973.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst4996.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5001.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5003.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5028.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5053.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5059.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5064.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5074.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5080.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5088.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5093.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5108.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5110.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5127.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5147.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5148.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5164.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5178.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5192.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5197.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5208.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5227.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5228.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5247.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5248.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5253.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5283.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5290.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5293.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5302.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5320.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5323.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5329.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5333.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5341.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5363.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5380.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5384.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5387.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5388.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5398.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5401.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5412.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5424.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5426.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5427.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5433.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5453.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5456.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5458.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5460.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5472.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5481.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5500.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5505.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5513.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5522.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5524.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5530.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5537.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5573.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5576.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5579.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5600.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5603.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5606.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5627.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5635.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5639.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5663.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5672.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5677.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5685.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5692.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5719.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5726.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5742.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5779.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5781.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5782.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5797.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5813.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5818.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5835.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5837.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5887.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5895.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5908.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5919.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5933.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5948.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5951.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5953.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5958.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5977.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5981.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5989.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5993.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5996.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst5997.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6031.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6068.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6092.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6094.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6098.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6110.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6113.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6119.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6121.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6123.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6136.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6143.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6146.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6163.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6183.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6192.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6193.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6195.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6197.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6199.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6215.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6235.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6254.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6260.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6261.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6262.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6263.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6275.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6287.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6312.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6314.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6319.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6321.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6341.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6348.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6361.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6368.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6373.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6377.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6384.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6397.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6404.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6407.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6418.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6420.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6439.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6454.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6455.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6488.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6490.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6506.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6512.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6535.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6549.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6561.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6563.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6579.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6588.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6591.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6595.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6603.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6606.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6619.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6624.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6632.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6633.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6658.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6661.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6668.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6679.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6692.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6696.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6716.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6723.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6724.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6734.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6740.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6752.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6758.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6778.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6792.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6799.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6800.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6801.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6803.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6806.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6864.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6880.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6883.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6905.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6907.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6935.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6941.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6947.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6948.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6956.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6965.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6974.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6977.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst6982.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7017.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7032.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7064.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7081.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7082.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7083.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7085.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7087.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7095.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7102.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7127.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7144.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7148.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7153.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7157.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7159.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7161.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7168.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7180.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7197.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7208.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7230.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7238.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7255.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7256.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7302.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7317.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7319.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7329.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7352.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7355.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7358.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7366.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7367.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7374.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7376.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7389.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7392.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7394.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7395.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7400.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7406.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7416.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7424.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7433.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7436.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7447.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7448.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7450.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7460.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7462.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7471.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7475.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7514.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7539.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7564.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7565.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7577.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7603.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7614.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7648.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7674.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7677.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7683.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7687.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7689.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7700.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7704.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7716.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7717.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7719.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7721.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7744.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7751.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7765.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7766.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7769.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7774.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7807.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7829.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7838.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7858.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7861.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7874.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7893.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7898.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7903.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7910.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7921.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7923.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7925.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7930.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7943.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7967.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7973.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7991.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst7995.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8003.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8004.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8024.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8025.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8028.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8029.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8058.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8070.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8089.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8097.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8104.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8107.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8116.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8119.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8121.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8122.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8124.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8125.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8157.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8173.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8174.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8199.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8208.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8214.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8215.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8224.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8232.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8263.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8274.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8277.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8278.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8282.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8284.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8297.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8303.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8307.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8312.xdti_16f_9t_96_ckmux21.xmux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8313.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8327.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8349.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8358.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8368.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8379.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8380.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8386.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8394.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8419.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8443.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8444.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8456.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8463.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8474.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8491.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8497.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8501.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8537.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8542.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8546.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8553.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8558.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8576.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8590.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8611.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8628.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8639.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8642.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8649.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8651.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8654.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8662.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8681.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8690.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8718.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8725.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8757.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8762.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8775.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8780.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8781.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8788.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8807.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8833.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8857.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8871.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8885.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8887.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8889.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8892.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8937.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8949.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8950.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8956.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst8972.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9002.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9015.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9026.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9041.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9055.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9060.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9071.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9092.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9093.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9096.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9102.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9112.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9131.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9142.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9143.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9147.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9158.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9159.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9170.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9174.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9206.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9210.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9229.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9238.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9239.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9246.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9253.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9255.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9256.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9257.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9264.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9267.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9274.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9276.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9280.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9284.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9287.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9301.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9319.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9331.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9332.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9363.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9364.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9366.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9369.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9383.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9400.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9411.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9416.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9456.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9466.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9475.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9478.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9481.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9487.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9499.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9522.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9523.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9524.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9529.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9534.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9544.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9582.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9589.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9615.xdti_16f_9t_96_mux21 69.44 100.00 8.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9639.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9665.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9670.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9673.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9674.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9690.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9691.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9693.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9725.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9738.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9756.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9759.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9760.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9768.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9777.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9779.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9785.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9790.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9794.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9797.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9826.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9835.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9836.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9871.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9883.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9913.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9937.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9941.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9947.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9978.xdti_16f_9t_96_mux21 86.11 100.00 58.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst9991.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10001.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10007.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10012.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10023.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10029.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10036.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10037.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10039.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10061.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10064.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10081.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10083.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10095.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10109.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10116.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10143.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10144.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10157.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10174.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10203.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10213.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10214.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10222.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10223.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10257.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10277.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10286.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10290.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10300.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10311.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10315.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10358.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10359.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10378.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10383.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10386.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10391.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10394.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10399.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10401.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10408.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10416.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10419.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10430.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10466.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10468.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10472.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10479.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10485.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10495.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10498.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10502.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10511.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10514.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10520.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10523.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10525.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10532.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10541.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10543.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10551.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10553.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10569.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10591.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10597.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10604.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10610.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10619.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10628.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10632.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10645.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10646.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10650.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10657.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10686.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10687.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10693.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10696.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10697.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10710.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10729.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10738.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10745.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10748.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10752.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10755.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10776.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10782.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10796.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10802.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10810.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10827.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10839.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10873.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10899.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10923.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10927.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10977.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10982.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst10998.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11022.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11023.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11024.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11033.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11036.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11045.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11057.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11072.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11088.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11104.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11119.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11124.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11164.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11168.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11171.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11187.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11189.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11209.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11211.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11222.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11239.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11253.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11278.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11304.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11307.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11313.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11334.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11349.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11352.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11359.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11361.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11364.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11387.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11398.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11407.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11412.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11426.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11457.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11465.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11490.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11491.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11499.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11503.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11506.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11521.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11535.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11548.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11553.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11588.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11589.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11604.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11624.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11626.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11630.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11643.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11647.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11656.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11659.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11664.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11667.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11676.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11682.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11699.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11707.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11738.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11739.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11744.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11779.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11780.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11785.xdti_16f_9t_96_mux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11801.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11807.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11838.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11848.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11856.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11884.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11894.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11905.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11906.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11909.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11932.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11933.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11941.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11944.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11945.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11954.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11977.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11978.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11986.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11994.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst11995.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12011.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12054.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12056.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12082.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12089.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12099.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12124.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12132.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12140.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12141.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12174.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12183.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12216.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12223.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12228.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12229.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12242.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12243.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12261.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12268.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12284.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12285.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12286.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12288.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12292.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12308.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12310.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12311.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12329.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12344.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12351.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12368.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12377.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12395.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12411.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12416.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12424.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12432.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12433.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12444.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12445.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12460.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12480.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12494.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12496.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12527.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12529.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12545.xdti_16f_9t_96_ckmux21.xmux21 44.44 50.00 33.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12548.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12557.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12574.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12586.xdti_16f_9t_96_mux21 38.89 50.00 16.67 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12593.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12595.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12606.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12609.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12619.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12629.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12631.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12642.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12644.xdti_16f_9t_96_mux21 36.11 50.00 8.33 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12645.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12649.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12650.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12651.xdti_16f_9t_96_ckmux21.xmux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12659.xdti_16f_9t_96_mux21 77.78 100.00 33.33 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12686.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12698.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12705.xdti_16f_9t_96_mux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12727.xdti_16f_9t_96_ckmux21.xmux21 88.89 100.00 66.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12733.xdti_16f_9t_96_mux21 72.22 100.00 16.67 100.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12741.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12744.xdti_16f_9t_96_mux21 50.00 50.00 50.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12766.xdti_16f_9t_96_mux21 33.33 50.00 0.00 50.00
config_ss_tb.DUT.memory_ss.ddr_wrapper.dti_tm16_phy.dti_tm16ffcd4lp4r2_18d_dq8_jm[3].xinst12777.xdti_16f_9t_96_mux21 83.33 100.00 50.00 100.00

Cond Coverage for Module : dti_mux21
TotalCoveredPercent
Conditions22100.00
Logical22100.00
Non-Logical00
Event00

 LINE       8107
 EXPRESSION (S ? D1 : D0)
             1
-1-Status
0Covered
1Covered
Toggle Coverage for Module : dti_mux21
TotalCoveredPercent
Totals 6 4 66.67
Total Bits 12 8 66.67
Total Bits 0->1 6 4 66.67
Total Bits 1->0 6 4 66.67

Ports 6 4 66.67
Port Bits 12 8 66.67
Port Bits 0->1 6 4 66.67
Port Bits 1->0 6 4 66.67

Port Details
NameToggleToggle 1->0Toggle 0->1Direction
VDD No No No INPUT
VSS No No No INPUT
Z Yes Yes Yes OUTPUT
D0 Yes Yes Yes INPUT
D1 Yes Yes Yes INPUT
S Yes Yes Yes INPUT

Branch Coverage for Module : dti_mux21
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 8107 2 2 100.00 



8107       assign Z = S ? D1 : D0;
                        -1-  
                        ==>  
                        ==>

Branches:
-1-Status
1 Covered
0 Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%